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Design and Implementation of a Hardware Level Content Networking Front End Device
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TitleDesign and Implementation of a Hardware Level Content Networking Front End Device
AuthorBuboltz, Jeremy Layne
KeywordsContent Networking
Front End Device
Hardware Implementation
AbstractThe bandwidth and speed of network connections are continually increasing. The speed increase in network technology is set to soon outpace the speed increase in CMOS technology. This asymmetrical growth is beginning to causing software applications that once worked with then current levels of network traffic to flounder under the new high data rates. Processes that were once executed in software now have to be executed, partially if not wholly in hardware. One such application that could benefit from hardware implementation is high layer routing. By allowing a network device to peer into higher layers of the OSI model, the device can scan for viruses, provide higher quality-of-service (QoS), and efficiently route packets. This thesis proposes an architecture for a device that will utilize hardware-level string matching to distribute incoming requests for a server farm. The proposed architecture is implemented in VHDL, synthesized, and laid out on an Altera FPGA.
AdviserKocak, Taskin
PublisherUniversity of Central Florida
DegreeM.S.Cp.E.
Degree DisciplineSchool of Electrical Engineering and Computer Science
Degree GrantorEngineering and Computer Science
Degree ProgramComputer Engineering MSCpE
Graduation Date2007-12-01
TypeMaster's thesis
Access LevelCampus - Allow Only UCF Community Access
RepositoryUniversity Archives
Repository CollectionElectronic Theses and Dissertations
IdentifierCFE0001888
Access Linkhttp://purl.fcla.edu/fcla/etd/CFE0001888

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