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SUSTAINABLE FAULT-HANDLING OF RECONFIGURABLE LOGIC USING THROUGHPUT-DRIVEN ASSESSMENT
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| Title | SUSTAINABLE FAULT-HANDLING OF RECONFIGURABLE LOGIC USING THROUGHPUT-DRIVEN ASSESSMENT |
| Author | Sharma, Carthik
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| Keywords | evolvable hardware
fault tolerance
group testing
organic systems
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| Abstract | A sustainable Evolvable Hardware (EH) system is developed for SRAM-based reconfigurable Field Programmable Gate Arrays (FPGAs) using outlier detection and group testing-based assessment principles. The fault diagnosis methods presented herein leverage throughput-driven, relative fitness assessment to maintain resource viability autonomously. Group testing-based techniques are developed for adaptive input-driven fault isolation in FPGAs, without the need for exhaustive testing or coding-based evaluation. The techniques maintain the device operational, and when possible generate validated outputs throughout the repair process. Adaptive fault isolation methods based on discrepancy-enabled pair-wise comparisons are developed. By observing the discrepancy characteristics of multiple Concurrent Error Detection (CED) configurations, a method for robust detection of faults is developed based on pairwise parallel evaluation using Discrepancy Mirror logic. The results from the analytical FPGA model are demonstrated via a self-healing, self-organizing evolvable hardware system. Reconfigurability of the SRAM-based FPGA is leveraged to identify logic resource faults which are successively excluded by group testing using alternate device configurations. This simplifies the system architect's role to definition of functionality using a high-level Hardware Description Language (HDL) and system-level performance versus availability operating point. System availability, throughput, and mean time to isolate faults are monitored and maintained using an Observer-Controller model. Results are demonstrated using a Data Encryption Standard (DES) core that occupies approximately 305 FPGA slices on a Xilinx Virtex-II Pro FPGA. With a single simulated stuck-at-fault, the system identifies a completely validated replacement configuration within three to five positive tests. The approach demonstrates a readily-implemented yet robust organic hardware application framework featuring a high degree of autonomous self-control. |
| Adviser | DeMara, Ronald
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| Publisher | University of Central Florida |
| Degree | Ph.D.
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| Degree Discipline | School of Electrical Engineering and Computer Science
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| Degree Grantor | Engineering and Computer Science
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| Degree Program | Computer Engineering PhD
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| Graduation Date | 2008-01-01 |
| Type | Doctoral dissertation
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| Access Level | Public - Allow Worldwide Access
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| Release Date | 2008-09-05 |
| Repository | University Archives
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| Repository Collection | Electronic Theses and Dissertations
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| Identifier | CFE0002329 |
| Access Link | http://purl.fcla.edu/fcla/etd/CFE0002329 |
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