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MINIMIZATION OF POWER DISSIPATION IN DIGITAL CIRCUITS USING PIPELINING AND A STUDY OF CLOCK GATING TECHNIQUE
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TitleMINIMIZATION OF POWER DISSIPATION IN DIGITAL CIRCUITS USING PIPELINING AND A STUDY OF CLOCK GATING TECHNIQUE
AuthorPanchangam, Ranganath
KeywordsDissertations, Academic -- Engineering and Computer Science
Engineering and Computer Science -- Dissertations, Academic
Clock gating
Digital circuits
Pipelining
Power dissipation
AbstractPower dissipation is one of the major design issues of digital circuits. The power dissipated by a circuit affects its speed and performance. Multiplier is one of the most commonly used circuits in the digital devices. There are various types of multipliers available depending upon the application in which they are used. In the present thesis report, the importance of power dissipation in today's digital technology is discussed and the various types and sources of power dissipation have been elaborated. Different types of multipliers have been designed which vary in their structure and amount of power dissipation. The concept of pipelining is explained and the reduction in the power dissipation of the multipliers after pipelining is experimentally determined. Clock gating is a very important technique used in the design of digital circuits to reduce power dissipation. Various types of clock gating techniques have been presented as a case study. The technology used in the simulation of these circuits is 0.35µm CMOS and the simulator used is SPECTRE S.
AdviserYuan, Jiann-Shiun
PublisherUniversity of Central Florida
DegreeM.S.
Degree DisciplineDepartment of Electrical and Computer Engineering
Degree GrantorEngineering and Computer Science
Degree ProgramElectrical and Computer Engineering
Graduation Date2004-08-01
TypeMaster's thesis
Access LevelPublic - Allow Worldwide Access
Release Date2005-01-31
RepositoryUniversity Archives
Repository CollectionElectronic Theses and Dissertations
IdentifierCFE0000130
Access Linkhttp://purl.fcla.edu/fcla/etd/CFE0000130

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